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The fast growth of the cloud interconnectivity is continuously driving the efficiency, performance, and reliability in cloud networking infrastructure. At Microsoft Research@198, we are exploring novel network technologies to empower next-generation cloud and AI infrastructure. We are looking to hire an intern to contribute to the design and development of an FPGA platform to drive our exploration.
The successful candidate will work within a leading multidisciplinary industrial research team revolutionizing the future sustainable cloud infrastructure. In this stimulating environment, they will have the opportunity to learn and grow digital hardware design and debug skills while testing and evaluating the entire networking system in the lab.
Qualifications
Required/minimum qualifications
- Being enrolled in a Master or PhD program of computer science, computer engineering, electrical and electronics engineering, or other related fields.
- Or in the last year of Bachelor’s degree in the related fields.
Other requirements
- Experience working on research projects related to digital hardware design
- Demonstrated experience in design and development cycle of FPGA- or ASIC- based hardware systems, i.e. from RTL coding to system-level testing and performance evaluation
- Thorough understanding of digital logic design concepts from system level to low level details
- Good RTL coding and debugging skills (Verilog/System Verilog preferred)
Preferred/additional qualifications
- Experience with network physical layer and gigabits transceivers on modern FPGAs.
- Experience with software programming (C/C++/Python)
Responsibilities
Successful candidates will be working in a small, multi-disciplinary team of experts from the fields of FPGAs, optics, networking, and distributed systems and will have an opportunity to get hands-on experiences of developing communication technologies for future connectivity solutions in data centers.
Candidates will be expected to implement a part of a larger FPGA design system, using RTL for design and verification, and perform experiments on a FPGA hardware to evaluate performance and behaviour of the system in the lab.
